Exemplary embodiments of the present invention relate generally to a semiconductor device, and more particularly, to a semiconductor memory device and a method for fabricating the same.
With broadening uses of mobile devices and continued miniaturization thereof, the efforts to highly integrate the semiconductor devices continue. In the case of a dynamic random access memory (DRAM) device or flash memory device, various attempts have been made to form more memory cells in a small area. The DRAM device comprises a transistor and a capacitor in its memory cell, and a known DRAM device comprises a transistor with a planar structure.
Also, a storage node contact is formed between a source region formed of the transistor and the capacitor to electrically connect the transistor to the capacitor. A drain region of the transistor is electrically connected to a bit line through a bit line contact. In a structure in which a capacitor is formed over the transistor with the planar structure, layers for signal transmission, such as word and bit lines are arranged between the transistor and the capacitor. There is a limitation in increasing the capacitance of the capacitor due to the space occupied by the layers. Moreover, if the width of a gate of the transistor with the planar structure is narrowed by 40 nm or less, the amount of body current that is a leakage current between source and drain regions may increase. Therefore, a vertical transistor with a vertical channel is being developed.
FIG. 1 is a cross-sectional view illustrating a vertical transistor.
Referring to FIG. 1, the vertical transistor 100 has a structure in which a drain region 112 is formed at a lower side of a silicon semiconductor substrate 110 and a source region 114 is formed at an upper side of the silicon semiconductor substrate 110. A channel region 116 is formed between the drain and source regions 112 and 114, and a gate insulating layer 118 and a gate electrode 120 are sequentially formed on a side of the silicon semiconductor substrate 110 in the channel region 116. In the case where the vertical transistor 100 is used as a switching element of a DRAM device, a bit line is connected to the drain region 112, and a storage node is connected to the source region 114. Since the bit line is arranged to be buried at a lower side of the silicon semiconductor substrate 110, a space in which the storage node is to be formed may increase compared with the DRAM device comprising the transistor with the planar structure, and accordingly, data storage ability may be improved even at a degree of high integration.
In order to form the vertical transistor described above, the drain region 112 is formed at the lower side of the silicon semiconductor substrate 110, but this process is not easy to perform. For example, before the drain region 112 is formed, a high-concentration doped region is formed on a lower side of the silicon semiconductor substrate 110, at which the drain region 112 is to be formed, and dopants in the doped region is diffused, thereby forming the drain region 112. However, with the degree of high integration of the semiconductor device, the size of the memory cell decreases, and thus it is not easy to precisely form the drain region 112.